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never stop thinking. microcontrollers data sheet, v1.0, apr. 2003 c164sv 16-bit single-chip microcontroller
edition 2003-04 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2003. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide. warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or system s with the express written approval of infineon technologies, if a failure of such co mponents can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support a nd/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
p r e l i m i n a r y microcontrollers data sheet, v1.0, apr. 2003 never stop thinking. c164sv 16-bit single-chip microcontroller
c164sv preliminary revision history: 2003-04 v1.0 previous version: --- page subjects (major chan ges since last revision) we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
data sheet 1 v1.0, 2003-04 preliminary c164sv 16-bit single-chip microcontroller c166 family c164sv ? high performance 16-bit cpu with 4-stage pipeline ? 80 ns instruction cycle time at 25 mhz cpu clock ? 400 ns multiplication (16 16 bit), 800 ns division (32 / 16 bit) ? enhanced boolean bit manipulation facilities ? additional instructions to support hll and operating systems ? register-based design with multiple variable register banks ? single-cycle context switching support ? 16 mbytes total linear address space for code and data ? 1024 bytes on-chip special function register area 16-priority-level interrupt system with 32 sources, sample-rate down to 40 ns 8-channel interrupt-driven single-cycle data transfer facilities via peripheral event controller (pec) clock generation via on-chip pll (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input on-chip memory modules ? 1 kbyte on-chip internal ram (iram) ? 16 kbytes on-chip program mask rom on-chip peripheral modules ? 8-channel 10-bit/12-bit a/d converter with programmable conversion time down to 7.8 s (10-bit) or 10.9 s (12-bit) ? 12-channel general purpose capture/compare unit (capcom2) ? capture/compare unit for flexible pwm signal generation (capcom6) (3/6 capture/compare channels and 1 compare channel) ? multi-functional general purpose timer unit with 3 timers ? synchronous/asynchronous serial channel (asc) ? high-speed synchronous serial channel (ssc) ? on-chip real time clock up to 64 kbytes external address space for code and data ? programmable external bus characteristics for different address ranges ? multiplexed external address/data bus with - 8-bit data bus width (2 kbytes address space, a10 ? a0, serial interfaces) - 16-bit data bus width (64 kbytes address space, a15 ? a0) idle, sleep, and power down modes with flexible power management programmable watchdog timer and oscillator watchdog up to 50 general purpose i/o lines supported by a large range of development tools like c-compilers, macro-assembler packages, emulators, evaluation boards, hll-debuggers, simulators, logic analyzer disassemblers, programming boards
c164sv data sheet 2 v1.0, 2003-04 preliminary on-chip bootstrap loader 64-pin tqfp package, 0.5 mm pitch this document describes several derivatives of the c164 group. table 1 enumerates these derivatives and summarizes the differences. as this document refers to all of these derivatives, some descriptions may not apply to a specific product. for simplicity all versions are referred to by the term c164sv throughout this document. note: the c164sv is compatible (pin-compatible and function-compatible) with the c164sm with reduced memory areas. table 1 c164sv derivative synopsis derivative 1) 1) this data sheet is valid for devices st arting with and including design step aa. program memory capcom6 can interf. operating frequency SAK-C164SV-2RF saf-c164sv-2rf 16 kbytes rom full function --- 20 mhz sak-c164sv-2r25f saf-c164sv-2r25f 16 kbytes rom full function --- 25 mhz
c164sv data sheet 3 v1.0, 2003-04 preliminary ordering information the ordering code for infineon microcontrolle rs provides an exact reference to the required product. this ordering code identifies: the derivative itself, i.e. its function set, the temperature range, and the supply voltage the package and the type of delivery. for the available ordering codes for the c164sv please refer to the ?product catalog microcontrollers? , which summarizes all available microcontroller variants. note: the ordering codes for mask-rom versions are defined for each product after verification of the respective rom code. introduction the c164sv derivatives of the infineon c166 family of full featured single-chip cmos microcontrollers are especially suited for co st sensitive applications. they combine high cpu performance (up to 12.5 million instru ctions per second) with high peripheral functionality and enhanced io-capabilities. they also provide clock generation via pll and various on-chip memory modules such as program rom and internal ram. figure 1 logic symbol mcl04954 v dd v ss xtal1 xtal2 port 0 16 bit port 1 16 bit port 8 4 bit port 5 8 bit rstin nmi v aref v agnd port 20 6 bit c164sv
c164sv data sheet 4 v1.0, 2003-04 preliminary pin configuration (top view) figure 2 table 2 on the pages below lists the possible assignments. mcp04955_4sv.vsd xtal2 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p5.7/an7/t4in v ss p5.6/an6/t2in p5.5/an5/t4eud p5.4/an4/t2eud p5.3/an3/t3in p0.13/ad13/mrst p0.14/ad14/mtsr p0.15/ad15/sclk v ss p0.8/ad8 p0.9/ad9 p0.10/ad10 p0.11/ad11/txd0 p0.12/ad12/rxd0 v dd v dd p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 nmi rstin p20.0/rd p20.1/w r p20.4/ale p20.5/ea v dd p20.12/rstout p1.0/cc60 p1.1/cout60 p1.2/cc61 p1.3/cout61 p1.4/cc62 p1.5/cout62 p1.6/cout63 p1.7/ctrap p1.8/cc6pos0/ex0in/cc28io p1.9/cc6pos1/ex1in/cc29io p1.10/cc6pos2/ex2in/cc30io p1.11/ex3in/t7in/cc31io v dd p20.8/clkout/fout v ss xtal1 v ss p1.12/cc24io p1.13/cc25io p1.14/cc26io p1.15/cc27io p8.0/cc16io p8.1/cc17io p8.2/cc18io p8.3/cc19io p5.0/an0 p5.1/an1 p5.2/an2/t3eud v agnd v aref c164sv
c164sv data sheet 5 v1.0, 2003-04 preliminary table 2 pin definitions and functions symbol pin no. input outp. function port0 p0h.7 p0h.6 p0h.5 p0h.4 p0h.3 p0h.2 p0h.1 p0h.0 p0l.7 p0l.6 p0l.5 p0l.4 p0l.3 p0l.2 p0l.1 p0l.0 8 9 10 11 12 13 14 15 18 19 20 21 22 23 24 25 io (i)/o i/o (i)/o i/o (i)/o i/o (i)/o i/o (i)/o o (i)/o (i)/o (i)/o i/o i/o i/o i/o i/o i/o i/o i/o port0 consists of the two 8- bit bidirectional i/o ports p0l and p0h. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. in case of an external bus configuration, port0 serves as the address (a) and address/data (ad) bus in multiplexed bus modes. a(d)15 most significant address(/data) line sclk ssc master clock output / slave clock input. a(d)14 address(/data) line mtsr ssc master-transmit/slave-receive outp./inp. a(d)13 address(/data) line mrst ssc master-receive/s lave-transmit inp./outp. a(d)12 address(/data) line rxd0 asc0 data input (async.) or inp./outp. (sync.) a(d)11 address(/data) line txd0 asc0 clock/data output (async./sync.) a(d)10 address(/data) line a(d)9 address(/data) line a(d)8 address(/data) line ad7 address/data line ad6 address/data line ad5 address/data line ad4 address/data line ad3 address/data line ad2 address/data line ad1 address/data line ad0 least significant address/data line nmi 26 i non-maskable interrupt input. a high to low transition at this pin causes the cpu to vector to the nmi trap routine. when the pwrdn (power down) instruction is executed, the nmi pin must be low in order to force the c164sv into power down mode. if nmi is high, when pwrdn is executed, the part will continue to run in normal mode. if not used, pin nmi should be pulled high externally.
c164sv data sheet 6 v1.0, 2003-04 preliminary rstin 27 i/o reset input with schmitt-trigger characteristics. a low level at this pin while the oscillator is running resets the c164sv. an internal pullup resistor permits power-on reset using only a capacitor connected to v ss . a spike filter suppresses input pulses <10 ns. input pulses >100 ns safely pass the filter. the minimum duration for a safe recognition should be 100 ns + 2 cpu clock cycles. in bidirectional reset mode (enabled by setting bit bdrsten in register syscon) the rstin line is internally pulled low for the duration of the internal reset sequence upon any reset (hw, sw, wdt). see note below this table. note: to let the reset configuration of port0 settle and to let the pll lock a reset duration of ca. 1 ms is recommended. table 2 pin definitions and functions (cont?d) symbol pin no. input outp. function
c164sv data sheet 7 v1.0, 2003-04 preliminary p20 p20.0 p20.1 p20.4 p20.5 p20.8 p20.12 28 29 30 31 34 35 io o o o i o o o port 20 is a 6-bit bidi rectional i/o port (no p20.5 output driver in the otp versions). it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. the following port 20 pins also serve for alternate functions: rd external memory read strobe, activated for every external instruction or data read access. wr external memory write strobe, activated for every external data write access. ale address latch enable output. can be used for latching the address into external memory or an address latch in the multiplexed bus modes. ea external access enable pin. a low level at this pin during and after reset forces the c164sv to latch the configuration from port0 and pin rd , and to begin instruction execution out of external memory. a high level forces the c164sv to latch the configuration from pins rd , ale, and wr , and to begin instruction execution out of the internal program memory. ?romless? versions must hav e this pin tied to ?0?. clkout system clock output (= cpu clock), fout programmable frequency output rstout internal reset indication output. this pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. rstout remains low until the einit (end of initiali zation) instruction is executed. table 2 pin definitions and functions (cont?d) symbol pin no. input outp. function
c164sv data sheet 8 v1.0, 2003-04 preliminary port1 p1l.0 p1l.1 p1l.2 p1l.3 p1l.4 p1l.5 p1l.6 p1l.7 p1h.0 p1h.1 p1h.2 p1h.3 p1h.4 p1h.5 p1h.6 p1h.7 36 37 38 39 40 41 42 43 44 45 46 47 52 53 54 55 io i/o o i/o o i/o o o i i i i/o i i i/o i i i/o i i i/o i/o i/o i/o i/o port1 consists of the two 8- bit bidirectional i/o ports p1l and p1h. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. the following port1 pins also serve for alt. functions: cc60 capcom6: input / output of channel 0 cout60 capcom6: output of channel 0 cc61 capcom6: input / output of channel 1 cout61 capcom6: output of channel 1 cc62 capcom6: input / output of channel 2 cout62 capcom6: output of channel 2 cout63 output of 10-bit compare channel ctrap capcom6: trap input ctrap is an input pin with an internal pullup resistor. a low level on this pin switches the capcom6 compare outputs to the logic level defined by software (if enabled). cc6pos0 capcom6: position 0 input, ex0in fast external interrupt 0 input, cc28io capcom2: cc28 capture inp./compare outp. cc6pos1 capcom6: position 1 input, ex1in fast external interrupt 1 input, cc29io capcom2: cc29 capture inp./compare outp. cc6pos2 capcom6: position 2 input, ex2in fast external interrupt 2 input, cc30io capcom2: cc30 capture inp./compare outp. ex3in fast external interrupt 3 input, t7in capcom2: timer t7 count input, cc31io capcom2: cc31 capture inp./compare outp. cc24io capcom2: cc24 capture inp./compare outp. cc25io capcom2: cc25 capture inp./compare outp. cc26io capcom2: cc26 capture inp./compare outp. cc27io capcom2: cc27 capture inp./compare outp. xtal2 xtal1 49 50 o i xtal2: output of the oscillator amplifier circuit. xtal1: input to the oscillator amplifier and input to the internal clock generator to clock the device from an external source, drive xtal1, while leaving xtal2 unconnected. minimum and maximum high/low and rise/fall times specified in the ac characteristics must be observed. table 2 pin definitions and functions (cont?d) symbol pin no. input outp. function
c164sv data sheet 9 v1.0, 2003-04 preliminary p8 p8.0 p8.1 p8.2 p8.3 56 57 58 59 io i/o i/o i/o i/o port 8 is a 4-bit bidirecti onal i/o port. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high- impedance state. port 8 outputs can be configured as push/ pull or open drain drivers. the following port 8 pins also serve for alternate functions: cc16io capcom2: cc16 capture inp./compare outp. cc17io capcom2: cc17 capture inp./compare outp. cc18io capcom2: cc18 capture inp./compare outp. cc19io capcom2: cc19 capture inp./compare outp. p5 p5.0 p5.1 p5.2 p5.3 p5.4 p5.5 p5.6 p5.7 62 63 64 1 2 3 4 5 i i i i i i i i i port 5 is an 8-bit input-only port with schmitt-trigger characteristic. the pins of port 5 also serve as analog input channels for the a/d converter, or they serve as timer inputs: an0 an1 an2, t3eud gpt1 timer t3 ext. up/down ctrl. inp. an3, t3in gpt1 timer t3 count input an4, t2eud gpt1 timer t5 ext. up/down ctrl. inp. an5, t4eud gpt1 timer t4 ext. up/down ctrl. inp. an6, t2in gpt1 timer t2 count input an7, t4in gpt1 timer t4 count input v agnd 60 ? reference ground for the a/d converter. v aref 61 ? reference voltage for the a/d converter. v dd 7, 16, 32, 48 ? digital supply voltage: +5 v during normal operation and idle mode. 2.5 v during power down mode. v ss 6, 17, 33, 51 ? digital ground. table 2 pin definitions and functions (cont?d) symbol pin no. input outp. function
c164sv data sheet 10 v1.0, 2003-04 preliminary note: the following behavior differences must be observed when the bidirectional reset is active: bit bdrsten in register syscon cannot be changed after einit and is cleared automatically after a reset. the reset indication flags always indicate a long hardware reset. the port0 configuration is treated as if it were a hardware reset. in particular, the bootstrap loader may be activated when p0l.4 is low. pin rstin may only be connected to external reset devices with an open drain output driver. a short hardware reset is extended to the duration of the internal reset sequence.
c164sv data sheet 11 v1.0, 2003-04 preliminary functional description the architecture of the c164sv comb ines advantages of both risc and cisc processors and of advanced peripheral subsystems in a very well-balanced way. in addition the on-chip memory blocks allow the design of compact systems with maximum performance. the following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the c164sv. note: all time specifications refer to a cpu clock of 25 mhz (see definition in the ac characteristics section). figure 3 block diagram the program memory, the internal ram (iram) and the set of generic peripherals are connected to the cpu via separate buses. a fourth bus, the xbus, connects external resources as well as additional on-chip resoures, the x-peripherals (see figure 3 ). c166-core cpu interrupt bus xtal mcb04323_4sv.vsd osc / pll rtc wdt 32 16 interrupt controller 16-level priority pec external instr. / data gpt1 t2 t3 t4 ssc brgen (spi) asc0 brgen (usart) adc 10-/12-bit 8 channels ccom2 t7 t8 ccom6 t12 t13 ebc xbus control external bus control iram dual port internal ram 1 kbyte progmem rom 16 kbytes data data 16 16 16 instr. / data port 0 6 16 8 port 5 port 1 port 20 on-chip xbus (16-bit demux) peripheral data bus 16 16 port 8 4
c164sv data sheet 12 v1.0, 2003-04 preliminary memory organization the memory space of the c164sv is confi gured in a von neumann architecture which means that code memory, data memory, registers and i/o ports are organized within the same linear address space which includes 16 mbytes. the entire memory space can be accessed bytewise or wordwise. particular portions of the on-chip memory have additionally been made directly bitaddressable. the c164sv incorporates 16 kbytes of on-chip mask-programmable rom (not in the rom-less derivative, of course) for code or constant data. the on-chip rom can be mapped either to segment 0 or segment 1. 1 kbyte of on-chip internal ram (iram) is provided as a storage for user defined variables, for the system stack, general pu rpose register banks and even for code. a register bank can consist of up to 16 wordwide (r0 to r15) and/or bytewide (rl0, rh0, ?, rl7, rh7) so-called general purpose registers (gprs). 1024 bytes (2 512 bytes) of the address space are reserved for the special function register areas (sfr space and esfr space). sfrs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. unused sfr addresses are reserved for future members of the c166 family. in order to meet the needs of designs where more memory is required than is provided on chip, up to 64 kbytes of external ram and/or rom can be connected to the microcontroller.
c164sv data sheet 13 v1.0, 2003-04 preliminary external bus controller all of the external memory accesses are per formed by a particular on-chip external bus controller (ebc). it can be programmed either to single chip mode when no external memory is required, or to one of two different external memory access modes, which are as follows: ? 16-bit addresses, 16-bit data, multiplexed ? 11-bit addresses, 8-bit data, multiplexed both addresses and data use port0 for input/output. important timing characteristics of the external bus interface (memory cycle time, memory tri-state time, length of ale and read write delay) have been made programmable to allow the user the adapti on of a wide range of different types of memories and external peripherals. in addition, up to 4 independent address windows may be defined (via register pairs addrselx / busconx) wh ich control the access to different resources with different bus characteristics. these address win dows are arranged hierarchically where buscon4 overrides buscon 3 and buscon2 overrides buscon1. all accesses to locations not covered by these 4 addr ess windows are controlled by buscon0. note: the programmable bus features and the window mechanism are standard features of the c166 architecture. due to the c164sv?s limited external address space, however, they can be utilized only to a small extend. the c164sv will preferably be used in single-chip mode. applications which require access to external resources such as peri pherals or small memories, will use the 8-bit data bus with 11-bit address bus in most cases. in this case the upper pins of port0 can be used for the serial interfaces. if a wider address or a 16-bit data bus is required the serial interfaces cannot be used.
c164sv data sheet 14 v1.0, 2003-04 preliminary central processing unit (cpu) the main core of the cpu consists of a 4-st age instruction pipeline, a 16-bit arithmetic and logic unit (alu) and dedicated sfrs. additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. based on these hardware provisions, most of the c164sv?s instructions can be executed in just one machine cycle which requires 2 cpu clocks (4 tcl). for example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. all multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 16 bit multiplication in 5 cycles and a 32 -/16-bit division in 10 cycles. another pipeline optimization, the so-called ?jump cache?, reduces the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle. figure 4 cpu block diagram
c164sv data sheet 15 v1.0, 2003-04 preliminary the cpu has a register context consisting of up to 16 wordwide gprs at its disposal. these 16 gprs are physically allocated within the on-chip ram area. a context pointer (cp) register determines the base address of the active register bank to be accessed by the cpu at any time. the number of register banks is only restricted by the available internal ram space. for easy parameter passing, a register bank may overlap others. a system stack of up to 512 words is provided as a storage for temporary data. the system stack is allocated in the on-chip ram area, and it is accessed by the cpu via the stack pointer (sp) register. two separat e sfrs, stkov and stkun, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. the high performance offered by the hardware implementation of the cpu can efficiently be utilized by a programmer via the highly efficient c164sv instruction set which includes the following instruction classes: ? arithmetic instructions ? logical instructions ? boolean bit manipulation instructions ? compare and loop control instructions ? shift and rotate instructions ? prioritize instruction ? data movement instructions ? system stack instructions ? jump and call instructions ? return instructions ? system control instructions ? miscellaneous instructions the basic instruction length is either 2 or 4 bytes. possible operand types are bits, bytes and words. a variety of direct, indirect or immediate addressing modes are provided to specify the required operands.
c164sv data sheet 16 v1.0, 2003-04 preliminary interrupt system with an interrupt response time within a ran ge from just 5 to 12 cpu clocks (in case of internal program execution), the c164sv is capable of reacting very fast to the occurrence of non-deterministic events. the architecture of the c164sv supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. any of t hese interrupt requests can be programmed to being serviced by the interrupt controller or by the peripheral event controller (pec). in contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ?stolen? from the current cpu activity to perform a pec service. a pec service implies a single byte or word data transfer between any two memory locations with an additional increment of either the pec source or the destination pointer. an individual pec transfer counter is implicity decremented for each pec service except when performing in the continuous transfer mode. when this counte r reaches zero, a standard interrupt is performed to the corresponding source related vector location. pec services are very well suited, for example, for supporting the transmission or reception of blocks of data. the c164sv has 8 pec channels each of which offers such fast interrupt-driven data transfer capabilities. a separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. via its related register, each source can be programmed to one of sixteen interrupt priority levels. once having been accepted by th e cpu, an interrupt service can only be interrupted by a higher prioritized service request. for the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. fast external interrupt inputs are provided to service external interrupts with high precision requirements. these fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). software interrupts are supported by means of the ?trap? instruction in combination with an individual trap (interrupt) number. table 3 shows all of the possible c164sv interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers. note: interrupt nodes which are not used by associated peripherals, may be used to generate software controlled interrupt requests by setting the respective interrupt request bit (xir).
c164sv data sheet 17 v1.0, 2003-04 preliminary table 3 c164sv interrupt nodes source of interrupt or pec service request request flag enable flag interrupt vector vector location trap number fast external interrupt 0 cc8ir cc8ie cc8int 00?0060 h 18 h fast external interrupt 1 cc9ir cc9ie cc9int 00?0064 h 19 h fast external interrupt 2 cc10ir cc10ie cc10int 00?0068 h 1a h fast external interrupt 3 cc11ir cc11ie cc11int 00?006c h 1b h gpt1 timer 2 t2ir t2ie t2int 00?0088 h 22 h gpt1 timer 3 t3ir t3ie t3int 00?008c h 23 h gpt1 timer 4 t4ir t4ie t4int 00?0090 h 24 h a/d conversion complete adcir adcie adcint 00?00a0 h 28 h a/d overrun error adeir adeie adeint 00?00a4 h 29 h asc0 transmit s0tir s0tie s0tint 00?00a8 h 2a h asc0 transmit buffer s0tbir s0tbie s0tbint 00?011c h 47 h asc0 receive s0rir s0rie s0rint 00?00ac h 2b h asc0 error s0eir s0eie s0eint 00?00b0 h 2c h ssc transmit sctir sctie sctint 00?00b4 h 2d h ssc receive scrir scrie scrint 00?00b8 h 2e h ssc error sceir sceie sceint 00?00bc h 2f h capcom register 16 cc16ir cc16ie cc16int 00?00c0 h 30 h capcom register 17 cc17ir cc17ie cc17int 00?00c4 h 31 h capcom register 18 cc18ir cc18ie cc18int 00?00c8 h 32 h capcom register 19 cc19ir cc19ie cc19int 00?00cc h 33 h capcom register 24 cc24ir cc24ie cc24int 00?00e0 h 38 h capcom register 25 cc25ir cc25ie cc25int 00?00e4 h 39 h capcom register 26 cc26ir cc26ie cc26int 00?00e8 h 3a h capcom register 27 cc27ir cc27ie cc27int 00?00ec h 3b h capcom timer 7 t7ir t7ie t7int 00?00f4 h 3d h capcom timer 8 t8ir t8ie t8int 00?00f8 h 3e h capcom6 interrupt cc6ir cc6ie cc6int 00?00fc h 3f h pll/owd and rtc xp3ir xp3ie xp3int 00?010c h 43 h capcom 6 timer 12 t12ir t12ie t12int 00?0134 h 4d h
c164sv data sheet 18 v1.0, 2003-04 preliminary capcom 6 timer 13 t13ir t13ie t13int 00?0138 h 4e h capcom 6 emergency cc6eir cc6eie cc6eint 00?013c h 4f h unassigned node xp0ir xp0ie xp0int 00?0100 h 40 h table 3 c164sv interrupt nodes (cont?d) source of interrupt or pec service request request flag enable flag interrupt vector vector location trap number
c164sv data sheet 19 v1.0, 2003-04 preliminary the c164sv also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ?hardware traps?. hardware traps cause immedi ate non-maskable system reacti on which is similar to a standard interrupt service (branching to a dedicated vector table location). the occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (tfr). except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. in turn, hardware trap services can normally not be interrupted by standard or pec interrupts. table 4 shows all of the possible exceptions or error conditions that can arise during run- time: table 4 hardware trap summary exception condition trap flag trap vector vector location trap number trap priority reset functions: ? hardware reset ? software reset ? w-dog timer overflow ? reset reset reset 00?0000 h 00?0000 h 00?0000 h 00 h 00 h 00 h iii iii iii class a hardware traps: ? non-maskable interrupt ? stack overflow ? stack underflow nmi stkof stkuf nmitrap stotrap stutrap 00?0008 h 00?0010 h 00?0018 h 02 h 04 h 06 h ii ii ii class b hardware traps: ? undefined opcode ? protected instruction fault ? illegal word operand access ? illegal instruction access ? illegal external bus access undopc prtflt illopa illina illbus btrap btrap btrap btrap btrap 00?0028 h 00?0028 h 00?0028 h 00?0028 h 00?0028 h 0a h 0a h 0a h 0a h 0a h i i i i i reserved ? ? [2c h ? 3c h ] [0b h ? 0f h ] ? software traps ? trap instruction ?? any [00?0000 h ? 00?01fc h ] in steps of 4 h any [00 h ? 7f h ] current cpu priority
c164sv data sheet 20 v1.0, 2003-04 preliminary the capture/compare unit capcom2 the general purpose capcom2 unit s upports generation and control of timing sequences on up to 12 channels with a maximum resolution of 16 tcl. the capcom units are typically used to handle high speed i/o tasks such as pulse and waveform generation, pulse width modulation (pmw), digital to analog (d/a) conversion, software timing, or time recording relative to external events. two 16-bit timers (t7/t8) with reload registers provide two independent time bases for the capture/compare register array. each dual purpose capture/compare register, which may be individually allocated to either capcom timer and programmed for capture or compare function, has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. when a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (?capture?d) into the capture/compare register in response to an external event at the port pin which is associated with this register. in addition, a specific interrupt r equest for this capture/compare register is generated. either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the tr iggering event. the contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers . when a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode. table 5 compare modes (capcom) compare modes function mode 0 interrupt-only compare mode; several compare interrupts per timer period are possible mode 1 pin toggles on each compare match; several compare events per timer period are possible mode 2 interrupt-only compare mode; only one compare interrupt per timer period is generated mode 3 pin set ?1? on match; pin reset ?0? on compare time overflow; only one compare event per timer period is generated double register mode two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible. registers cc16 & cc24 ? pin cc16io registers cc17 & cc25 ? pin cc17io registers cc18 & cc26 ? pin cc18io registers cc19 & cc27 ? pin cc19io
c164sv data sheet 21 v1.0, 2003-04 preliminary the capture/compare unit capcom6 the capcom6 unit supports generation and cont rol of timing sequences on up to three 16-bit capture/compare channels plus one 10-bit compare channel. in compare mode the capcom6 unit provi des two output signals per channel which have inverted polarity and non-overlapping pulse transitions. the compare channel can generate a single pwm output signal and is further used to modulate the capture/ compare output signals. in capture mode the contents of compare timer 12 is stored in the capture registers upon a signal transition at pins ccx. compare timers t12 (16-bit) and t13 (10-bit) are free running timers which are clocked by the prescaled cpu clock. figure 5 capcom6 block diagram for motor control applications both subuni ts may generate versatile multichannel pwm signals which are basically either controlled by compare timer 12 or by a typical hall sensor pattern at the interrupt inputs (block commutation). control cc channel 0 cc60 cc channel 1 cc61 cc channel 2 cc62 mcb04109 prescaler offset register t12of compare timer t12 16-bit period register t12p mode select register cc6msel trap register port control logic control register ctcon compare register cmp13 prescaler compare timer t13 10-bit period register t13p block commutation control cc6mcon.h cc60 cout60 cc61 cout61 cc62 cout62 ctrap cc6pos0 cc6pos1 cc6pos2 f cpu f cpu cout63 the timer registers (t12, t13) are not directly accessible. the period and offset registers are loading a value into the timer registers.
c164sv data sheet 22 v1.0, 2003-04 preliminary general purpose timer (gpt) unit the gpt unit represents a very flexible mu ltifunctional timer/counter structure which may be used for many different time rela ted tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. the gpt unit incorporates three 16-bit timers. each timer may operate independently in a number of different modes, or may be concatenated with another timer. each of the three timers t2, t3, t4 of module gpt1 can be configured individually for one of four basic modes of operation, which are timer, gated timer, counter, and incremental interface mode. in timer mode, the input clock for a timer is derived from the cpu clock, divided by a programmable prescaler, while counter mode allows a timer to be clocked in reference to external events. pulse width or duty cycle measurement is supported in gated timer mode, where the operation of a timer is controlled by the ?gat e? level on an external input pin. for these purposes, each timer has one associated port pin (txin) which serves as gate or clock input. the maximum resolution of the timers in module gpt1 is 16 tcl. the count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (txeud) to facilitate e.g. position tracking. in incremental interface mode the gpt1 ti mers (t2, t3, t4) can be directly connected to the incremental position sensor signals a and b via their respective inputs txin and txeud. direction and count signals are inter nally derived from these two input signals, so the contents of the respective timer tx co rresponds to the sensor position. the third position sensor signal top0 can be connected to an interrupt input. timer t3 has an output toggle latch (t3otl) which changes its state on each timer over- flow/underflow. the state of this latch may be used internally to clock timers t2 and t4 for measuring long time periods with high resolution. in addition to their basic operating modes, timers t2 and t4 may be configured as reload or capture registers for timer t3. when used as capture or reload registers, timers t2 and t4 are stopped. the contents of timer t3 is captured into t2 or t4 in response to a signal at their associated input pins (txin) . timer t3 is reloaded with the contents of t2 or t4 triggered either by an external signal or by a selectable state transition of its toggle latch t3otl.
c164sv data sheet 23 v1.0, 2003-04 preliminary figure 6 block diagram of gpt1 t3 mode control 2 n : 1 f cpu 2 n : 1 f cpu t2 mode control gpt1 timer t2 reload capture 2 n : 1 f cpu t4 mode control gpt1 timer t4 reload capture gpt1 timer t3 t3otl u/d t2eud t2in t3in t3eud t4in t4eud toggle ff u/d u/d interrupt request (t2ir) interrupt request (t3ir) interrupt request (t4ir) other timers mct04825_4 n = 3 ? 10
c164sv data sheet 24 v1.0, 2003-04 preliminary real time clock the real time clock (rtc) module of the c164sv consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer t14, and the 32-bit rtc timer (accessible via registers rtch and rtcl). the rtc module is directly clocked with the on-chip oscillator frequency divided by 32 via a separate clock driver ( f rtc = f osc /32) and is therefore independent from the selected clock generation mode of the c164sv. all timers count up. the rtc module can be used for different purposes: system clock to determine the current time and date cyclic time based interrupt 48-bit timer for long term measurements figure 7 rtc block diagram note: the registers associated with the rtc are not affected by a reset in order to maintain the correct system time even when intermediate rese ts are executed. mcd04432 t14rel t14 8:1 rtc f rtcl rtch interrupt request reload
c164sv data sheet 25 v1.0, 2003-04 preliminary a/d converter for analog signal measurement, a 10-bit/12-bit a/d converter with 8 multiplexed input channels and a sample and hold circuit has be en integrated on-chip. it uses the method of successive approximation. the sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry. overrun error detection/protection is provided for the conversion result register (addat): either an interrupt request will be generated when the result of a previous conversion has not been read from the result r egister at the time the next conversion is complete, or the next conversion is suspended in such a case until the previous result has been read. for applications which require less than 8 analog input channels, the remaining channel inputs can be used as digital input port pins. the a/d converter of the c164sv supports fo ur different conversion modes. in the standard single channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. in the single channel continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. in the auto scan mode, the analog levels on a prespecified number of channels (standard or extension) are sequentially sampled and converted. in the auto scan continuous mode, the numb er of prespecified channels is repeatedly sampled and converted. in addition, the conversion of a specific channel can be inserted (injected) into a running sequence without di sturbing this sequence. this is called channel injection mode. the peripheral event controller (pec) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interr upt routines for each data transfer. after each reset and also during normal operation the adc automatically performs calibration cycles. this automatic self-calib ration constantly adjusts the converter to changing operating conditions (e.g. temperature) and compensates process variations. these calibration cycles are part of the conversion cycle, so they do not affect the normal operation of the a/d converter. in order to decouple analog inputs from digi tal noise and to avoid input trigger noise those pins used for analog input can be disc onnected from the digital io or input stages under software control. this can be selected for each pin separately via register p5didis (port 5 digital input disable).
c164sv data sheet 26 v1.0, 2003-04 preliminary serial channels serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an asynchronous/synchronous serial channel ( asc0 ) and a high-speed synchronous serial channel ( ssc ). the asc0 is upward compatible with the serial ports of the infineon 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 781 kbit/s and half-duplex synchronous communication at up to 3.1 mbit/s (@ 25 mhz cpu clock). a dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. for transmission, reception and error handling 4 separate interrupt vectors are provided. in asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. for multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake up bit mode). in synchronous mode, the asc0 transmits or re ceives bytes (8 bits) synchronously to a shift clock which is generated by the asc0. the asc0 always shifts the lsb first. a loop back option is available for testing purposes. a number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. a pari ty bit can automatically be generated on transmission or be checked on reception. fram ing error detection allows to recognize data frames with missing stop bits. an overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. the ssc supports full-duplex synchronous communication at up to 6.25 mbit/s (@ 25 mhz cpu clock). it may be configured so it interfaces with serially linked peripheral components. a dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. for transmission, reception and error handling 3 separate interrupt vectors are provided. the ssc transmits or receives characters of 2 ? 16 bits length synchronously to a shift clock which can be generated by the ssc (master mode) or by an external master (slave mode). the ssc can start shifting with the lsb or with the msb and allows the selection of shifting and latching clock edges as well as the clock polarity. a number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. transmit and receive error supervise the correct handling of the data buffer. phase and baudrate error detect incorrect serial data.
c164sv data sheet 27 v1.0, 2003-04 preliminary watchdog timer the watchdog timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. the watchdog timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the einit (end of initialization) instruction has been executed. thus, the chip?s st art-up procedure is always monitored. the software has to be designed to service the watchdog timer bef ore it overflows. if, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardware reset and pulls the rstout pin low in order to allow external hardware components to be reset. the watchdog timer is a 16-bi t timer, clocked with the system clock divided by 2/4/128/ 256. the high byte of the watchdog timer register can be set to a prespecified reload value (stored in wdtrel) in order to allow further variation of the monitored time interval. each time it is serviced by the application software, the high byte of the watchdog timer is reloaded. thus, time intervals between 20 s and 336 ms can be monitored (@ 25 mhz). the default watchdog timer interval after reset is 5.24 ms (@ 25 mhz). parallel ports the c164sv provides up to 50 i/o lines which are organized into four input/output ports and one input port. all port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. the i/o ports are true bidirectional ports which are switched to high impedance state when configured as inputs. the output drivers of po rt 8 can be configured (pin by pin) for push/ pull operation or open-drain operation via a control register. during the internal reset, all port pins are configured as inputs. all port lines have programmable alternate input or output functions associated with them. all port lines that are not used for thes e alternate functions may be used as general purpose io lines. port0 may be used as address and data lines when accessing external memory. also the serial interfaces asc0 and ssc use the upper pins of p0h. ports p1l, p1h, and p8 are associated with the capture inputs or compare outputs of the capcom units and/or serve as external interrupt inputs. port 5 is used for the analog input channels to the a/d converter or timer control signals. port 20 includes the bus control signals rd , wr , ale, the configuration input ea , the the system control output rstout , and the system clock output clkout (or the programmable frequency output fout). the edge characteristics (transition time) and driver characteristics (output current) of the c164sv?s port drivers can be selected via the port output control registers (poconx).
c164sv data sheet 28 v1.0, 2003-04 preliminary oscillator watchdog the oscillator watchdog (owd) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). for this operation the pll provides a clock signal which is used to superv ise transitions on the oscillator clock. this pll clock is independent from the xtal1 clock. when the expected oscillator clock transitions are missing the owd activates the pll unlock/owd interrupt node and supplies the cpu with the pll clock signal. under these circumstances the pll will oscillate with its basic frequency. in direct drive mode the pll base frequency is used directly ( f cpu = 2 ? 5 mhz). in prescaler mode the pll base frequency is divided by 2 ( f cpu = 1 ? 2.5 mhz). note: the cpu clock source is only swit ched back to the oscillator clock after a hardware reset. the oscillator watchdog can be disabled by setting bit owddis in register syscon. in this case (owddis = ?1?) the pll remains idle and provides no clock signal, while the cpu clock signal is derived directly from the o scillator clock or via prescaler or sdd. also no interrupt request will be generated in case of a missing oscillator clock. note: at the end of a reset bit owddis reflects the inverted level of pin rd at that time. thus the oscillator watchdog may also be disabled via hardware by (externally) pulling the rd line low upon a reset, similar to the standard reset configuration via port0.
c164sv data sheet 29 v1.0, 2003-04 preliminary power management the c164sv provides several means to control the power it consumes either at a given time or averaged over a certain timespan. three mechanisms can be used (partly in parallel): power saving modes switch the c164sv into a special operating mode (control via instructions). idle mode stops the cpu while the peripherals can continue to operate. sleep mode and power down mode stop all clock signals and all operation (rtc may optionally continue running). sleep mode can be terminated by external interrupt signals. clock generati on management controls the distribution and the frequency of internal and external clock signal s (control via register syscon2). slow down mode lets the c164sv run at a cpu clock frequency of f osc /1 ? 32 (half for prescaler operation) which drastically reduces the consumed power. the pll can be optionally disabled while operating in slow down mode. external circuitry can be controlled via the programmable frequency output fout. peripheral management permits temporary disabling of peripheral modules (control via register syscon3). each peripheral can separately be disabled/enabled. a group control option disables a major part of the peripheral set by setting one single bit. the on-chip rtc supports intermittend operation of the c164sv by generating cyclic wakeup signals. this offers full performance to quickly react on action requests while the intermittend sleep phases greatly reduce the average pow er consumption of the system.
c164sv data sheet 30 v1.0, 2003-04 preliminary instruction set summary table 6 lists the instructions of the c164sv in a condensed way. the various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditio nal execution of instructions, and the opcodes for each instruction can be found in the ?c166 family instruction set manual? . this document also provides a deta iled description of each instruction. table 6 instruction set summary mnemonic description bytes add(b) add word (byte) operands 2 / 4 addc(b) add word (byte) operands with carry 2 / 4 sub(b) subtract word (byte) operands 2 / 4 subc(b) subtract word (byte) operands with carry 2 / 4 mul(u) (un)signed multiply direct gpr by direct gpr (16-16-bit) 2 div(u) (un)signed divide register mdl by direct gpr (16-/16-bit) 2 divl(u) (un)signed long divide reg. md by direct gpr (32-/16-bit) 2 cpl(b) complement direct word (byte) gpr 2 neg(b) negate direct word (byte) gpr 2 and(b) bitwise and, (word/byte operands) 2 / 4 or(b) bitwise or, (word/byte operands) 2 / 4 xor(b) bitwise xor, (word/byte operands) 2 / 4 bclr clear direct bit 2 bset set direct bit 2 bmov(n) move (negated) direct bit to direct bit 4 band, bor, bxor and/or/xor direct bit with direct bit 4 bcmp compare direct bit to direct bit 4 bfldh/l bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data 4 cmp(b) compare word (byte) operands 2 / 4 cmpd1/2 compare word data to gpr and decrement gpr by 1/2 2 / 4 cmpi1/2 compare word data to gpr and increment gpr by 1/2 2 / 4 prior determine number of shift cycles to normalize direct word gpr and store result in direct word gpr 2 shl / shr shift left/right direct word gpr 2 rol / ror rotate left/right direct word gpr 2 ashr arithmetic (sign bit) shift right direct word gpr 2
c164sv data sheet 31 v1.0, 2003-04 preliminary mov(b) move word (byte) data 2 / 4 movbs move byte operand to word operand with sign extension 2 / 4 movbz move byte operand to word operand with zero extension 2 / 4 jmpa, jmpi, jmpr jump absolute/indirect/relative if condition is met 4 jmps jump absolute to a code segment 4 j(n)b jump relative if direct bit is (not) set 4 jbc jump relative and clear bit if direct bit is set 4 jnbs jump relative and set bit if direct bit is not set 4 calla, calli, callr call absolute/indirect/relative subroutine if condition is met 4 calls call absolute subroutine in any code segment 4 pcall push direct word register onto system stack and call absolute subroutine 4 trap call interrupt service routine via immediate trap number 2 push, pop push/pop direct word register onto/from system stack 2 scxt push direct word register onto system stack and update register with word operand 4 ret return from intra-segment subroutine 2 rets return from inter-segment subroutine 2 retp return from intra-segment subroutine and pop direct word register from system stack 2 reti return from interrupt service subroutine 2 srst software reset 4 idle enter idle mode 4 pwrdn enter power down mode (supposes nmi -pin being low) 4 srvwdt service watchdog timer 4 diswdt disable watchdog timer 4 einit signify end-of-initialization on rstout -pin 4 atomic begin atomic sequence 2 extr begin extended register sequence 2 extp(r) begin extended page (and register) sequence 2 / 4 exts(r) begin extended segment (and register) sequence 2 / 4 nop null operation 2 table 6 instruction set summary (cont?d) mnemonic description bytes
c164sv data sheet 32 v1.0, 2003-04 preliminary special function registers overview table 7 lists all sfrs which are implemented in the c164sv in alphabetical order. the following markings assist in classifying the listed registers: ? b ? in the ?name? column marks bit-addressable sfrs. ? e ? in the ?physical address? column marks ( e )sfrs within the extended sfr-space . ? m ? in the ?physical address? column marks sfrs without short 8-bit address. an sfr can be specified via its individual mnemonic name. depending on the selected addressing mode, an sfr can be accessed via its physical address (using the data page pointers), or via its short 8-bit address (without using the data page pointers). table 7 c164sv registers, ordered by name name physical address 8-bit addr. description reset value adcic b ff98 h cc h a/d converter end of conversion interrupt control register 0000 h adcon b ffa0 h d0 h a/d converter control register 0000 h addat fea0 h 50 h a/d converter result register 0000 h addat2 f0a0 h e 50 h a/d converter 2 result register 0000 h addrsel1 fe18 h 0c h address select register 1 0000 h addrsel2 fe1a h 0d h address select register 2 0000 h addrsel3 fe1c h 0e h address select register 3 0000 h addrsel4 fe1e h 0f h address select register 4 0000 h adeic b ff9a h cd h a/d converter overrun error interrupt control register 0000 h buscon0 b ff0c h 86 h bus configuration register 0 0000 h buscon1 b ff14 h 8a h bus configuration register 1 0000 h buscon2 b ff16 h 8b h bus configuration register 2 0000 h buscon3 b ff18 h 8c h bus configuration register 3 0000 h buscon4 b ff1a h 8d h bus configuration register 4 0000 h cc10ic b ff8c h c6 h external interrupt 2 control register 0000 h cc11ic b ff8e h c7 h external interrupt 3 control register 0000 h cc16 fe60 h 30 h capcom register 16 0000 h cc16ic b f160 h e b0 h capcom reg. 16 interrupt ctrl. reg. 0000 h cc17 fe62 h 31 h capcom register 17 0000 h cc17ic b f162 h e b1 h capcom reg. 17 interrupt ctrl. reg. 0000 h
c164sv data sheet 33 v1.0, 2003-04 preliminary cc18 fe64 h 32 h capcom register 18 0000 h cc18ic b f164 h e b2 h capcom reg. 18 interrupt ctrl. reg. 0000 h cc19 fe66 h 33 h capcom register 19 0000 h cc19ic b f166 h e b3 h capcom reg. 19 interrupt ctrl. reg. 0000 h cc20 fe68 h 34 h capcom register 20 0000 h cc21 fe6a h 35 h capcom register 21 0000 h cc22 fe6c h 36 h capcom register 22 0000 h cc23 fe6e h 37 h capcom register 23 0000 h cc24 fe70 h 38 h capcom register 24 0000 h cc24ic b f170 h e b8 h capcom reg. 24 interrupt ctrl. reg. 0000 h cc25 fe72 h 39 h capcom register 25 0000 h cc25ic b f172 h e b9 h capcom reg. 25 interrupt ctrl. reg. 0000 h cc26 fe74 h 3a h capcom register 26 0000 h cc26ic b f174 h e ba h capcom reg. 26 interrupt ctrl. reg. 0000 h cc27 fe76 h 3b h capcom register 27 0000 h cc27ic b f176 h e bb h capcom reg. 27 interrupt ctrl. reg. 0000 h cc28 fe78 h 3c h capcom register 28 0000 h cc29 fe7a h 3d h capcom register 29 0000 h cc30 fe7c h 3e h capcom register 30 0000 h cc31 fe7e h 3f h capcom register 31 0000 h cc60 fe30 h 18 h capcom 6 register 0 0000 h cc61 fe32 h 19 h capcom 6 register 1 0000 h cc62 fe34 h 1a h capcom 6 register 2 0000 h cc6cic b f17e h e bf h capcom 6 interrupt control register 0000 h cc6eic b f188 h e c4 h capcom 6 emergency interr. ctrl. reg. 0000 h cc6mcon b ff32 h 99 h capcom 6 mode control register 00ff h cc6mic b ff36 h 9b h capcom 6 mode interrupt ctrl. reg. 0000 h cc6msel f036 h e 1b h capcom 6 mode select register 0000 h cc8ic b ff88 h c4 h external interrupt 0 control register 0000 h cc9ic b ff8a h c5 h external interrupt 1 control register 0000 h table 7 c164sv registers, ordered by name (cont?d) name physical address 8-bit addr. description reset value
c164sv data sheet 34 v1.0, 2003-04 preliminary ccm4 b ff22 h 91 h capcom mode control register 4 0000 h ccm5 b ff24 h 92 h capcom mode control register 5 0000 h ccm6 b ff26 h 93 h capcom mode control register 6 0000 h ccm7 b ff28 h 94 h capcom mode control register 7 0000 h cmp13 fe36 h 1b h capcom 6 timer 13 compare reg. 0000 h cp fe10 h 08 h cpu context pointer register fc00 h csp fe08 h 04 h cpu code segment pointer register (8 bits, not directly writeable) 0000 h ctcon b ff30 h 98 h capcom 6 compare timer ctrl. reg. 1010 h dp0h b f102 h e 81 h p0h direction control register 00 h dp0l b f100 h e 80 h p0l direction control register 00 h dp1h b f106 h e 83 h p1h direction control register 00 h dp1l b f104 h e 82 h p1l direction control register 00 h dp20 b ffb6 h db h port 20 direction control register 1000 h dp8 b ffd6 h eb h port 8 direction control register 00 h dpp0 fe00 h 00 h cpu data page pointer 0 reg. (10 bits) 0000 h dpp1 fe02 h 01 h cpu data page pointer 1 reg. (10 bits) 0001 h dpp2 fe04 h 02 h cpu data page pointer 2 reg. (10 bits) 0002 h dpp3 fe06 h 03 h cpu data page pointer 3 reg. (10 bits) 0003 h exicon b f1c0 h e e0 h external interrupt control register 0000 h exisel b f1da h e ed h external interrupt source select reg. 0000 h focon b ffaa h d5 h frequency output control register 0000 h idchip f07c h e 3e h identifier xxxx h idmanuf f07e h e 3f h identifier 1820 h idmem f07a h e 3d h identifier x008 h idmem2 f076 h e 3b h identifier 0000 h idprog f078 h e 3c h identifier xxxx h isnc b f1de h e ef h interrupt subnode control register 0000 h mdc b ff0e h 87 h cpu multiply divide control register 0000 h mdh fe0c h 06 h cpu multiply divide reg. ? high word 0000 h table 7 c164sv registers, ordered by name (cont?d) name physical address 8-bit addr. description reset value
c164sv data sheet 35 v1.0, 2003-04 preliminary mdl fe0e h 07 h cpu multiply divide reg. ? low word 0000 h odp8 b f1d6 h e eb h port 8 open drain control register 00 h ones b ff1e h 8f h constant value 1?s register (read only) ffff h p0h b ff02 h 81 h port 0 high reg. (upper half of port0) 00 h p0l b ff00 h 80 h port 0 low reg. (lower half of port0) 00 h p1h b ff06 h 83 h port 1 high reg. (upper half of port1) 00 h p1l b ff04 h 82 h port 1 low reg. (lower half of port1) 00 h p20 b ffb4 h da h port 20 register (6 bits) 0000 h p5 b ffa2 h d1 h port 5 register (read only) xxxx h p5didis b ffa4 h d2 h port 5 digital input disable register 0000 h p8 b ffd4 h ea h port 8 register (4 bits) 00 h pecc0 fec0 h 60 h pec channel 0 control register 0000 h pecc1 fec2 h 61 h pec channel 1 control register 0000 h pecc2 fec4 h 62 h pec channel 2 control register 0000 h pecc3 fec6 h 63 h pec channel 3 control register 0000 h pecc4 fec8 h 64 h pec channel 4 control register 0000 h pecc5 feca h 65 h pec channel 5 control register 0000 h pecc6 fecc h 66 h pec channel 6 control register 0000 h pecc7 fece h 67 h pec channel 7 control register 0000 h pocon0h f082 h e 41 h port p0h output control register 0011 h pocon0l f080 h e 40 h port p0l output control register 0011 h pocon1h f086 h e 43 h port p1h output control register 0011 h pocon1l f084 h e 42 h port p1l output control register 0011 h pocon20 f0aa h e 55 h port p20 output control register 0000 h pocon8 f092 h e 49 h port p8 output control register 0022 h psw b ff10 h 88 h cpu program status word 0000 h rp0h b f108 h e 84 h system startup config. reg. (rd. only) xx h rstcon b f1e0 h m --- reset control register 00xx h rtch f0d6 h e 6b h rtc high register no rtcl f0d4 h e 6a h rtc low register no table 7 c164sv registers, ordered by name (cont?d) name physical address 8-bit addr. description reset value
c164sv data sheet 36 v1.0, 2003-04 preliminary s0bg feb4 h 5a h serial channel 0 baud rate generator reload register 0000 h s0con b ffb0 h d8 h serial channel 0 control register 0000 h s0eic b ff70 h b8 h serial channel 0 error interrupt ctrl. reg. 0000 h s0rbuf feb2 h 59 h serial channel 0 receive buffer reg. (read only) xxxx h s0ric b ff6e h b7 h serial channel 0 receive interrupt control register 0000 h s0tbic b f19c h e ce h serial channel 0 transmit buffer interrupt control register 0000 h s0tbuf feb0 h 58 h serial channel 0 transmit buffer reg. (write only) 0000 h s0tic b ff6c h b6 h serial channel 0 transmit interrupt control register 0000 h sp fe12 h 09 h cpu system stack pointer register fc00 h sscbr f0b4 h e 5a h ssc baudrate register 0000 h ssccon b ffb2 h d9 h ssc control register 0000 h ssceic b ff76 h bb h ssc error interrupt control register 0000 h sscrb f0b2 h e 59 h ssc receive buffer xxxx h sscric b ff74 h ba h ssc receive interrupt control register 0000 h ssctb f0b0 h e 58 h ssc transmit buffer 0000 h ssctic b ff72 h b9 h ssc transmit interrupt control register 0000 h stkov fe14 h 0a h cpu stack overflow pointer register fa00 h stkun fe16 h 0b h cpu stack underflow pointer register fc00 h syscon b ff12 h 89 h cpu system configuration register 1) 0xx0 h syscon1 b f1dc h e ee h cpu system configuration register 1 0000 h syscon2 b f1d0 h e e8 h cpu system configuration register 2 0000 h syscon3 b f1d4 h e ea h cpu system configuration register 3 0000 h t12ic b f190 h e c8 h capcom 6 timer 12 interrupt ctrl. reg. 0000 h t12of f034 h e 1a h capcom 6 timer 12 offset register 0000 h table 7 c164sv registers, ordered by name (cont?d) name physical address 8-bit addr. description reset value
c164sv data sheet 37 v1.0, 2003-04 preliminary t12p f030 h e 18 h capcom 6 timer 12 period register 0000 h t13ic b f198 h e cc h capcom 6 timer 13 interrupt ctrl. reg. 0000 h t13p f032 h e 19 h capcom 6 timer 13 period register 0000 h t14 f0d2 h e 69 h rtc timer 14 register no t14rel f0d0 h e 68 h rtc timer 14 reload register no t2 fe40 h 20 h gpt1 timer 2 register 0000 h t2con b ff40 h a0 h gpt1 timer 2 control register 0000 h t2ic b ff60 h b0 h gpt1 timer 2 interrupt control register 0000 h t3 fe42 h 21 h gpt1 timer 3 register 0000 h t3con b ff42 h a1 h gpt1 timer 3 control register 0000 h t3ic b ff62 h b1 h gpt1 timer 3 interrupt control register 0000 h t4 fe44 h 22 h gpt1 timer 4 register 0000 h t4con b ff44 h a2 h gpt1 timer 4 control register 0000 h t4ic b ff64 h b2 h gpt1 timer 4 interrupt control register 0000 h t7 f050 h e 28 h capcom timer 7 register 0000 h t78con b ff20 h 90 h capcom timer 7 and 8 ctrl. reg. 0000 h t7ic b f17a h e bd h capcom timer 7 interrupt ctrl. reg. 0000 h t7rel f054 h e 2a h capcom timer 7 reload register 0000 h t8 f052 h e 29 h capcom timer 8 register 0000 h t8ic b f17c h e be h capcom timer 8 interrupt ctrl. reg. 0000 h t8rel f056 h e 2b h capcom timer 8 reload register 0000 h tfr b ffac h d6 h trap flag register 0000 h trcon b ff34 h 9a h capcom 6 trap enable ctrl. reg. 00xx h wdt feae h 57 h watchdog timer register (read only) 0000 h wdtcon ffae h d7 h watchdog timer control register 2) 00xx h xp0ic b f186 h e c3 h unassigned interrupt control reg. 0000 h xp3ic b f19e h e cf h pll/rtc interrupt control register 0000 h zeros b ff1c h 8e h constant value 0?s register (read only) 0000 h 1) the system configur ation is selected during reset. 2) the reset value depends on the indicated reset source. table 7 c164sv registers, ordered by name (cont?d) name physical address 8-bit addr. description reset value
c164sv data sheet 38 v1.0, 2003-04 preliminary absolute maximum ratings note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during absolute maximum rating overload conditions ( v in > v dd or v in < v ss ) the voltage on v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. table 8 absolute maximum rating parameters parameter symbol limit values unit notes min. max. storage temperature t st -65 150 c? junction temperature t j -40 150 c under bias voltage on v dd pins with respect to ground ( v ss ) v dd -0.5 6.5 v ? voltage on any pin with respect to ground ( v ss ) v in -0.5 v dd + 0.5 v ? input current on any pin during overload condition ? -10 10 ma ? absolute sum of all input currents during overload condition ? ? |100| ma ? power dissipation p diss ?1.5w?
c164sv data sheet 39 v1.0, 2003-04 preliminary operating conditions the following operating conditions must not be exceeded in order to ensure correct operation of the c164sv. all parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. table 9 operating condition parameters parameter symbol limit values unit notes min. max. digital supply voltage v dd 4.5 5.5 v active mode, f cpumax = 25 mhz 2.5 1) 1) output voltages and output currents will be reduced when v dd leaves the range defined for active mode. 5.5 v powerdown mode digital ground voltage v ss 0 v reference voltage overload current i ov ? 5 ma per pin 2)3) 2) overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. v ov > v dd + 0.5 v or v ov < v ss - 0.5 v). the absolute sum of input overload currents on all pins may not exceed 50 ma . the supply voltage must remain within the specified limits. proper operation is not guaranteed if overload conditions occur on functional pins line xtal1, rd , wr , etc. 3) not 100% tested, guaranteed by design and characterization. absolute sum of overload currents | i ov | ?50ma 3) external load capacitance c l ? 100 pf pin drivers in default mode 4) 4) the timing is valid for pin drivers operating in default current mode (selected after reset). reducing the output current may lead to increased delays or reduced driving capability ( c l ). ambient temperature t a 070 c sab-c164sv ? -40 85 c saf-c164sv ? -40 125 c sak-c164sv ?
c164sv data sheet 40 v1.0, 2003-04 preliminary parameter interpretation the parameters listed in the following partly represent the characteristics of the c164sv and partly its demands on the system. to aid in interpreting the parameters right, when evaluating them for a design, they are marked in column ?symbol?: cc ( c ontroller c haracteristics): the logic of the c164sv will provide signals with the respective characteristics. sr ( s ystem r equirement): the external system must provide signals wi th the respective characteristics to the c164sv. dc characteristics (operating conditions apply) 1) parameter symbol limit values unit test conditions min. max. input low voltage (ttl, all except xtal1) v il sr -0.5 0.2 v dd - 0.1 v? input low voltage xtal1 v il2 sr -0.5 0.3 v dd v? input high voltage (ttl, all except rstin , xtal1) v ih sr 0.2 v dd + 0.9 v dd + 0.5 v? input high voltage rstin (when operated as input) v ih1 sr 0.6 v dd v dd + 0.5 v? input high voltage xtal1 v ih2 sr 0.7 v dd v dd + 0.5 v? output low voltage 2) v ol cc ? 1.0 v i ol i olmax 3) ?0.45v i ol i olnom 3)4) output high voltage 5) v oh cc v dd - 1.0 ?v i oh i ohmax 3) v dd - 0.45 ?v i oh i ohnom 3)4) input leakage current (port 5) i oz1 cc ? 200 na 0 v < v in < v dd input leakage current (all other) i oz2 cc ? 500 na 0.45 v < v in < v dd rstin inactive current 6) i rsth 7) ?-10 a v in = v ih1 rstin active current 6) i rstl 8) -100 ? a v in = v il rd /wr inact. current 9) i rwh 7) ?-40 a v out = 2.4 v rd /wr active current 9) i rwl 8) -500 ? a v out = v olmax
c164sv data sheet 41 v1.0, 2003-04 preliminary ale inactive current 9) i alel 7) ?40 a v out = v olmax ale active current 9) i aleh 8) 500 ? a v out = 2.4 v port0 configuration current 10) i p0h 7) ?-10 a v in = v ihmin i p0l 8) -100 ? a v in = v ilmax xtal1 input current i il cc ? 20 a0 v < v in < v dd pin capacitance 11) (digital inputs/outputs) c io cc ? 10 pf f = 1 mhz t a = 25 c 1) keeping signal levels within the levels specified in this table, ensures operation without overload conditions. for signal levels outside these specifications also refer to the specification of the overload current i ov . 2) for pin rstin this specification is only valid in bidirectional reset mode. 3) the maximum deliverable output current of a port driv er depends on the selected output driver mode, see table 10 , current limits for port output drivers . the limit for pin groups must be respected. 4) as a rule, with decreasing output current the output levels approach the respective supply level ( v ol v ss , v oh v dd ). however, only the levels for nominal output currents are guaranteed. 5) this specification is not valid for outputs which are sw itched to open drain mode. in this case the respective output will float and the voltage results from the external circuitry. 6) these parameters describe the rstin pullup, which equals a resistance of ca. 50 to 250 k ? . 7) the maximum current may be drawn while the respective signal line remains inactive. 8) the minimum current must be drawn in order to drive the respective signal line active. 9) this specification is valid during reset and during adapt-mode. 10) this specification is valid during reset if required for configuration, and during adapt-mode. 11) not 100% tested, guaranteed by design and characterization. table 10 current limits for port output drivers port output driver mode maximum output current ( i olmax , - i ohmax ) 1) 1) an output current above | i oxnom | may be drawn from up to three pins at the same time. for any group of 16 neighboring port output pins the total output current in each direction ( i ol and - i oh ) must remain below 50 ma. nominal output current ( i olnom , - i ohnom ) strong driver 10 ma 2.5 ma medium driver 4.0 ma 1.0 ma weak driver 0.5 ma 0.1 ma dc characteristics (cont?d) (operating conditions apply) 1) parameter symbol limit values unit test conditions min. max.
c164sv data sheet 42 v1.0, 2003-04 preliminary power consumption c164sv (operating conditions apply) parameter sym- bol limit values unit test conditions min. max. power supply current (active) with all peripherals active i dd ?1 + 1.8 f cpu ma rstin = v il f cpu in [mhz] 1) idle mode supply current with all peripherals active i idx ?1 + 0.9 f cpu ma rstin = v ih1 f cpu in [mhz] 1) idle mode supply current with all peripherals deactivated, pll off, sdd factor = 32 i ido 2) ? 500 + 50 f osc arstin = v ih1 f osc in [mhz] 1) sleep and power-down mode supply current with rtc running i pdr 2) ? 200 + 25 f osc a v dd = v ddmax f osc in [mhz] 3) sleep and power-down mode supply current with rtc disabled i pdo ?25 a v dd = v ddmax 3) 1) the supply current is a function of the operating frequency. this dependency is illustrated in figure 9 . these parameters are tested at v ddmax and maximum cpu clock with all outputs disconnected and all inputs at v il or v ih . 2) this parameter is determined mainly by the current consumed by the oscillator (see figure 8 ). this current, however, is influenced by the external oscillator circuitry (crystal, capacitors). the valu es given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry. 3) this parameter is tested including leakage currents. all inputs (including pins configured as inputs) at 0 v to 0.1 v or at v dd - 0.1 v to v dd , all outputs (including pins configured as outputs) disconnected.
c164sv data sheet 43 v1.0, 2003-04 preliminary figure 8 idle and power down supply cu rrent as a function of oscillator frequency mcd04433 0 f osc pdomax i 4 8 12 16 0 250 mhz a 500 750 1000 1250 1500 pdrmax i idotyp i idomax i
c164sv data sheet 44 v1.0, 2003-04 preliminary figure 9 supply/idle current as a function of operating frequency i [ma] f cpu [mhz] 10 15 20 25 i dd5max i dd5typ i idx5max i idx5typ 20 40 60 80 100
c164sv data sheet 45 v1.0, 2003-04 preliminary ac characteristics definition of internal timing the internal operation of the c164sv is controlled by the internal cpu clock f cpu . both edges of the cpu clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. the specification of the external timing (a c characteristics) therefore depends on the time between two consecutive edges of the cpu clock, called ?tcl? (see figure 10 ). figure 10 generation mechan isms for the cpu clock the cpu clock signal f cpu can be generated from the oscillator clock signal f osc via different mechanisms. the duration of tcls and their variation (and also the derived external timing) depends on the used mechanism to generate f cpu . this influence must be regarded when calculating the timings for the c164sv. note: the example for pll operation shown in figure 10 refers to a pll factor of 4. the used mechanism to generate the basic cp u clock is selected by bitfield clkcfg in register rp0h.7-5. upon a long hardware reset register rp0h is loaded with the logic levels present on the upper half of port0 (p0h), i.e. bitfield clkcfg represents the logic levels on pins mct04338 f osc f cpu phase locked loop operation tcl f osc f cpu direct clock drive f osc f cpu prescaler operation tcl tcl tcl tcl tcl
c164sv data sheet 46 v1.0, 2003-04 preliminary p0.15-13 (p0h.7-5). register rp0h can be loaded from the upper half of register rstcon under software control. table 11 associates the combinations of these three bits with the respective clock generation mode. prescaler operation when prescaler operation is configured (clkcfg = 001 b ) the cpu clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. the frequency of f cpu is half the frequency of f osc and the high and low time of f cpu (i.e. the duration of an individual tcl) is defined by the period of the input clock f osc . the timings listed in the ac characterist ics that refer to tcls therefore can be calculated using the period of f osc for any tcl. phase locked loop when pll operation is configured (via clkcfg) the on-chip phase locked loop is enabled and provides the cpu clock (see table 11 ). the pll multiplies the input frequency by the factor f which is selected via the combination of bits rp0h.7-5 (i.e. f cpu = f osc f ). with every f ?th transition of f osc the pll circuit synchronizes the cpu clock to the input clock. this synchronization is done smoothly, i.e. the cpu clock frequency does not change abruptly. table 11 c164sv clock generation modes clkcfg 1) (rp0h.7-5) 1) please note that pin p0.15 (corresponding to rp0h.7) is inverted in emulation mode, and thus also in ehm. cpu frequency f cpu = f osc f external clock input range 2) 2) the external clock input range refers to a cpu clock range of 10 ? 25 mhz. notes 11 1 f osc 4 2.5 to 6.25 mhz default configuration 110 f osc 3 3.33 to 8.33 mhz ? 101 f osc 2 5 to 12.5 mhz ? 100 f osc 5 2 to 5 mhz ? 011 f osc 1 1 to 25 mhz direct drive 3) 3) the maximum frequency depends on the duty cycle of the external clock signal. 010 f osc 1.5 6.66 to 16.66 mhz ? 001 f osc / 2 2 to 50 mhz cpu clock via prescaler 000 f osc 2.5 4 to 10 mhz ?
c164sv data sheet 47 v1.0, 2003-04 preliminary due to this adaptation to the input clock the frequency of f cpu is constantly adjusted so it is locked to f osc . the slight variation causes a jitter of f cpu which also effects the duration of individual tcls. the timings listed in the ac characteristics that refer to tcls therefore must be calculated using the minimum tcl that is possible under the respective circumstances. the actual minimum value for tcl depends on the jitter of the pll. as the pll is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one tcl is lower than for one single tcl (see formula and figure 11 ). for a period of n tcl the minimum value is computed using the corresponding deviation d n : ( n tcl) min = n tcl nom - d n ; d n [ns] = (13.3 + n 6.3)/ f cpu [mhz], where n = number of consecutive tcls and 1 n 40. so for a period of 3 tcls @ 25 mhz (i.e. n = 3): d 3 = (13.3 + 3 6.3)/25 = 1.288 ns, and (3tcl) min = 3tcl nom - 1.288 ns = 58.7 ns (@ f cpu = 25 mhz). this is especially important for bus cycles us ing waitstates and e.g. for the operation of timers, serial interfaces, etc. for all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the pll jitter is neglectible. note: for all periods longer than 40 tcl the n = 40 value can be used (see figure 11 ). figure 11 approximated maximum accumulated pll jitter mcd04455 n max. jitter d n 1 10 20 30 ns 26.5 110 20 40 this approximated formula is valid for 1 n 40 and 10 mhz f cpu 25 mhz. 10 mhz 16 mhz 20 mhz 25 mhz 30 < ? < ? < ? < ?
c164sv data sheet 48 v1.0, 2003-04 preliminary direct drive when direct drive is configured (clkcfg = 011 b ) the on-chip phase locked loop is disabled and the cpu clock is directly driven from the internal oscillator with the input clock signal. the frequency of f cpu directly follows the frequency of f osc so the high and low time of f cpu (i.e. the duration of an individual tcl) is defined by the duty cycle of the input clock f osc . the timings listed below that refer to tcls therefore must be calculated using the minimum tcl that is possible under the res pective circumstances. this minimum value can be calculated via the following formula: tcl min = 1/ f osc dc min (dc = duty cycle) for two consecutive tcls the dev iation caused by the duty cycle of f osc is compensated so the duration of 2tcl is always 1/ f osc . the minimum value tcl min therefore has to be used only once for timings that require an odd number of tcls (1, 3, ?). timings that require an even number of tcls (2, 4, ?) may use the formula 2tcl = 1/ f osc .
c164sv data sheet 49 v1.0, 2003-04 preliminary ac characteristics external clock drive xtal1 (operating conditions apply) figure 12 external clock drive xtal1 note: if the on-chip oscillator is used toget her with a crystal, the oscillator frequency is limited to a range of 4 mhz to 16 mhz. it is strongly recommended to measure the oscillation allowance (or margin) in the final target system (layout) to determine the optimum parameters for the oscillator operation. please refer to the limits specified by the crystal supplier. when driven by an external clock signal it will accept the specified frequency range. operation at lower input frequencies is possible but is guaranteed by design only (not 100% tested). table 12 external clock drive characteristics parameter symbol direct drive 1:1 prescaler 2:1 pll 1:n unit min. max. min. max. min. max. oscillator period t osc sr 40 ? 20 ? 60 1) 1) the minimum and maximum oscillator periods for pll operation depend on the selected cpu clock generation mode. please see respective table above. 500 1) ns high time 2) 2) the clock input signal must reach the defined levels v il2 and v ih2 . t 1 sr 20 3) 3) the minimum high and low time refers to a duty cycle of 50%. the maximum operating frequency ( f cpu ) in direct drive mode depends on the du ty cycle of the clock input signal. ?6?10?ns low time 2) t 2 sr 20 3) ?6?10?ns rise time 2) t 3 sr?8?5?10ns fall time 2) t 4 sr?8?5?10ns mct02534 3 t 4 t v ih2 v il v dd 0.5 1 t 2 t osc t
c164sv data sheet 50 v1.0, 2003-04 preliminary a/d converter characteristics (operating conditions apply) table 13 a/d converter characteristics parameter symbol limit values unit test conditions min. max. analog reference supply v aref sr 4.0 v dd + 0.1 v analog reference ground v agnd sr v ss - 0.1 v ss + 0.2 v ? analog input voltage range v ain sr v agnd v aref v 1) 1) v ain may exceed v agnd or v aref up to the absolute ma ximum ratings. however, the conversion result in these cases will be x000 h or x3ff h , respectively. basic clock frequency f bc 0.5 6.25 mhz 2) 2) the limit values for f bc must not be exceeded when selecting the cpu frequency and the adctc setting. conversion time 3) 3) this parameter includes the sample time t s , the time for determining the digital result and the time to load the result register with the conversion result. values for the basic clock t bc depend on programming and can be taken from table 14 . this parameter depends on the adc control logic. it is not a real maximum va lue, but rather a fixum. t c10 cc ? 40 t bc + t s + 2 t cpu ? 10-bit conv. t cpu = 1 / f cpu t c12 cc ? 46 t bc + t s + 2 t cpu ? 12-bit conv. 4) t cpu = 1 / f cpu 4) for 12-bit conversions the cpu clo ck frequency must be limited to f cpu 20 mhz to achieve the specified tue limits. calibration time after reset t cal cc ? 3328 t bc ? 5) 5) during the reset calibration conversions can be executed (with the current accuracy). the time required for these conversions is added to the total reset calibration time. total unadjusted error tue cc ? 2 lsb 10-bit conv. 6)7) 6) tue is tested at v aref = v dd +0.1v, v agnd = 0 v. it is guaranteed by design for all other voltages within the defined voltage range. the specified tue is guaranteed only if the absolute sum of input overload currents on port 5 pins (see i ov specification) does not exceed 10 ma. during the reset calibration sequence the tue may reach twice the indicated maximum value. 4 lsb 12-bit conv. 6) internal resistance of reference voltage source r aref sr ? t bc / 60 - 0.25 k ? t bc in [ns] 8)9) internal resistance of analog source r asrc sr ? t s / 450 - 0.25 k ? t s in [ns] 9)10) adc input capacitance c ain cc ? 33 pf 9)
c164sv data sheet 51 v1.0, 2003-04 preliminary sample time and conversion time of the c164sv?s a/d converter are programmable. table 14 should be used to calculate the above timings. the limit values for f bc must not be exceeded when selecting adctc. timing example for 10-bit conversion: assumptions: f cpu = 25 mhz (i.e. t cpu = 40 ns), adctc = 00 b , adstc = 00 b . basic clock f bc = f cpu /4 = 6.25 mhz, i.e. t bc = 160 ns. sample time t s = t bc 8 = 1280 ns. conversion 10-bit t c10 = t s + 40 t bc + 2 t cpu = (1280 + 6400 + 80) ns = 7.8 s. timing example for 12-bit conversion: assumptions: f cpu = 20 mhz (i.e. t cpu = 50 ns), adctc = 00 b , adstc = 00 b . basic clock f bc = f cpu /4 = 5.0 mhz, i.e. t bc = 200 ns. sample time t s = t bc 8 = 1600 ns. conversion 10-bit t c10 = t s + 40 t bc + 2 t cpu = (1600 + 8000 + 100) ns = 9.7 s. conversion 12-bit t c12 = t s + 46 t bc + 2 t cpu = (1600 + 9200 + 100) ns = 10.9 s. 7) if the analog reference supply voltage exceeds the power supply voltage by up to 0.2 v (i.e. v aref = v dd + 0.2 v) the maximum tu e is increased to 3 lsb. this range is not 100% tested. 8) during the conversion the adc?s capacitance must be repeatedly charged or discharged. the internal resistance of the reference voltage source must allow the capacitance to reach it s respective voltage level within each conversion step. the maximum internal resistance results from the programmed conversion timing. 9) not 100% tested, guaranteed by design and characterization. 10) during the sample time the input capacitance c ain can be charged/discharged by the external source. the internal resistance of the analog source must allow th e capacitance to reach its final voltage level within t s . after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. values for the sample time t s depend on programming and can be taken from table 14 . table 14 a/d converter computation table adcon.15|14 (adctc) a/d converter basic clock f bc adcon.13|12 (adstc) sample time t s 00 f cpu / 4 00 t bc 8 01 f cpu / 2 01 t bc 16 10 f cpu / 16 10 t bc 32 11 f cpu / 8 11 t bc 64
c164sv data sheet 52 v1.0, 2003-04 preliminary testing waveforms figure 13 input ou tput waveforms figure 14 float waveforms mca04414 2.4 v 0.45 v 1.8 v 0.8 v 1.8 v 0.8 v test points ac inputs during testing are driven at 2.4 v for a logic ?1? and 0.45 v for a logic ?0?. timing measurements are made at ih v min for a logic ?1? and v il max for a logic ?0?. mca00763 - 0.1 v + 0.1 v + 0.1 v - 0.1 v reference for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, but begins to float when a 100 mv change from the loaded oh v timing points load v v load oh v v ol / v ol level occurs ( i oh ol i / = 20 ma) .
c164sv data sheet 53 v1.0, 2003-04 preliminary memory cycle variables the timing tables below use three variables which are derived from the busconx registers and represent the special characte ristics of the programmed memory cycle. the following table describes, how these variables are to be computed. note: please respect the maximum operating frequency of the respective derivative. ac characteristics table 15 memory cycle variables description symbol values ale extension t a tcl memory cycle time waitstates t c 2tcl (15 - ) memory tristate time t f 2tcl (1 - ) multiplexed bus (operating conditions apply) ale cycle time = 6 tcl + 2 t a + t c + t f (120 ns at 25 mhz cpu clock without waitstates) parameter symbol max. cpu clock = 25 mhz variable cpu clock 1 / 2tcl = 1 to 25 mhz unit min. max. min. max. ale high time t 5 cc 10 + t a ?tcl - 10 + t a ?ns address setup to ale t 6 cc 4 + t a ?tcl - 16 + t a ?ns address hold after ale t 7 cc 10 + t a ?tcl - 10 + t a ?ns ale falling edge to rd , wr (with rw-delay) t 8 cc 10 + t a ?tcl - 10 + t a ?ns ale falling edge to rd , wr (no rw-delay) t 9 cc -10 + t a ? -10 + t a ?ns address float after rd , wr (with rw-delay) t 10 cc?6?6ns address float after rd , wr (no rw-delay) t 11 cc ? 26 ? tcl + 6 ns rd , wr low time (with rw-delay) t 12 cc 30 + t c ? 2tcl - 10 + t c ?ns
c164sv data sheet 54 v1.0, 2003-04 preliminary rd , wr low time (no rw-delay) t 13 cc 50 + t c ? 3tcl - 10 + t c ?ns rd to valid data in (with rw-delay) t 14 sr ? 20 + t c ? 2tcl - 20 + t c ns rd to valid data in (no rw-delay) t 15 sr ? 40 + t c ? 3tcl - 20 + t c ns ale low to valid data in t 16 sr ? 40 + t a + t c ? 3tcl - 20 + t a + t c ns address to valid data in t 17 sr ? 50 + 2 t a + t c ? 4tcl - 30 + 2 t a + t c ns data hold after rd rising edge t 18 sr0?0?ns data float after rd t 19 sr ? 26 + t f ? 2tcl - 14 + t f ns data valid to wr t 22 cc 20 + t c ? 2tcl - 20 + t c ?ns data hold after wr t 23 cc 26 + t f ? 2tcl - 14 + t f ?ns ale rising edge after rd , wr t 25 cc 26 + t f ? 2tcl - 14 + t f ?ns address hold after rd , wr t 27 cc 26 + t f ? 2tcl - 14 + t f ?ns multiplexed bus (cont?d) (operating conditions apply) ale cycle time = 6 tcl + 2 t a + t c + t f (120 ns at 25 mhz cpu clock without waitstates) parameter symbol max. cpu clock = 25 mhz variable cpu clock 1 / 2tcl = 1 to 25 mhz unit min. max. min. max.
c164sv data sheet 55 v1.0, 2003-04 preliminary figure 15 external memory cycle: multiplexed bus, with read/write delay, normal ale (a10-a8) data in data out address address t 10 address ale bus read cycle rd bus write cycle wr t 5 t 16 t 17 t 6 t 7 t 25 t 27 t 18 t 19 t 14 t 12 t 10 t 22 t 23 t 12 t 8 t 8
c164sv data sheet 56 v1.0, 2003-04 preliminary figure 16 external memory cycle: multiplexed bus, with read/write delay, extended ale data out address data in address t 10 address ale (a10-a8) bus read cycle rd bus write cycle wr t 5 t 16 t 17 t 6 t 7 t 25 t 27 t 18 t 19 t 14 t 12 t 10 t 22 t 23 t 12 t 8 t 8
c164sv data sheet 57 v1.0, 2003-04 preliminary figure 17 external memory cycle: multiplexed bus, no read/write delay, normal ale data out address address data in address ale (a10-a8) bus read cycle rd bus write cycle wr t 5 t 16 t 17 t 6 t 7 t 25 t 27 t 18 t 19 t 15 t 13 t 22 t 23 t 13 t 9 t 9 t 11 t 11
c164sv data sheet 58 v1.0, 2003-04 preliminary figure 18 external memory cycle: multiplexed bus, no read/w rite delay, extended ale data out address data in address address ale (a10-a8) bus read cycle rd bus write cycle wr t 5 t 16 t 17 t 6 t 7 t 25 t 27 t 18 t 19 t 15 t 13 t 22 t 23 t 13 t 9 t 9 t 11 t 11
c164sv data sheet 59 v1.0, 2003-04 preliminary ac characteristics figure 19 clkout timing notes 1) cycle as programmed, including mctc waitstates (example shows 0 mctc ws). 2) the leading edge of the respective command depends on rw-delay. 3) multiplexed bus modes have a mux waitstate added afte r a bus cycle, and an addi tional mttc waitstate may be inserted here. for a multiplexed bus with mttc waitst ate this delay is 2 clkout cycles. 4) the next external bus cycle may start here. clkout (operating conditions apply) parameter symbol max. cpu clock = 25 mhz variable cpu clock 1 / 2tcl = 1 to 25 mhz unit min. max. min. max. clkout cycle time t 29 cc 40 40 2tcl 2tcl ns clkout high time t 30 cc 14 ? tcl - 6 ? ns clkout low time t 31 cc 10 ? tcl - 10 ? ns clkout rise time t 32 cc?4?4ns clkout fall time t 33 cc?4?4ns clkout rising edge to ale falling edge t 34 cc 0 + t a 10 + t a 0 + t a 10 + t a ns clkout ale t 30 t 34 mux/tristate 3) t 32 t 33 t 29 running cycle 1) t 31 command rd , wr 2) 4)
c164sv data sheet 60 v1.0, 2003-04 preliminary package outlines figure 20 p-tqfp-64-8 ( plastic metric quad flat package ) gpp09297 does not include plastic or metal protrusion of 0.25 max. per side 4x 64 1 index marking 0.08 d a 10 1) 12 -0.03 +0.07 0.2 0.5 7.5 a-b d 64x c 0.2 0.2 b a-b a-b d d h 0.1 c m 0.05 1.4 1.6 max . 0.08 0.05 0.15 4x h 0.6 7? max. 0.15 +0.03 -0.06 12 10 1) 1) y ou can find all of our packages, sorts of packing and others in our i nfineon internet page ?products?: http://www.infineon.com/products . dimensions in mm s md = surface mounted device
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